In many systems, expansion devices along expansion busses that allow communication with the system processor add capabilities and functions. A common example of these expansion devices is circuits on expansion boards, or cards, that can be inserted into a backplane of a computing system. The expansion bus provides communication between the new card and the system processor. A common example of a bus protocol used in this situation is a Peripheral Component Interconnect (PCI) bus.
The PCI bus is linked to the system bus upon which resides the system memory, the system processor and other system components by a device referred to here as a PCI bridge. In the case of more than one expansion bus, bridges may exist between the expansion busses that are generally referred to as PCI-to-PCI bridges, or P2P bridges. As used here, the term bridge may be used to refer to either type of bridge. Multiple P2P bridges may exist between the expansion card and the system bus.
In most PCI implementations, the PCI card desires to transmit data to the system memory. The PCI card transmits the data desired to the system memory through a bridge. When the PCI card has completed its transmission of the data, it transmits an interrupt along a command path to the processor. The command path is generally much faster than the path taken by the data, referred to here as the data path.
For example, if the data transfer from the card is complete, the data may have been transferred to the bridge between the PCI device and the system memory. The bridge may be handling transactions for several different PCI devices and the data may be temporarily stored in a buffer until it can be transmitted to the system memory. This is just one example of latencies in the data path. The result is that the processor receives the interrupt prior to the data being in memory. The processor may issue a read request for the address of the data and then stall until all of the data arrives at the address. This reduces the processor efficiency, as the processor essentially becomes idle while waiting on the data.
In one approach, a ‘false’ or ‘dummy’ PCI read is issued to the device when the interrupt is received at the microprocessor. When the PCI device receives the read request, it transfers its data to the system memory. When that transfer is complete, the processor is assured of having all of the necessary data in the system memory. While this may alleviate some of the problem, there is still a stall that occurs during the processing of the dummy read cycle.